SM320DM6446-HIREL_15 Datasheet, PDF (27/228 Pages) Texas Instruments – Digital Media System-on-Chip

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SM320DM6446
Digital Media System-on-Chip
SPRS607A – JUNE 2009 – REVISED JUNE 2009
SIGNAL
NAME
EM_CS4/
GPIO9/
VLYNQ_SCRUN
EM_CS5/
GPIO8/
VLYNQ_CLOCK
EM_R/W/
INTRQ/
HR/W
EM_WAIT/
(RDY/BSY)/
IORDY/
HRDY
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
EM_BA[0]/
DA0/
HINT
EM_BA[1]/
DA1/
GPIO52
EM_A[21]/
GPIO10/
VLYNQ_TXD0
EM_A[20]/
GPIO11/
VLYNQ_RXD0
EM_A[19]/
GPIO12/
VLYNQ_TXD1
EM_A[18]/
GPIO13/
VLYNQ_RXD1
EM_A[17]/
GPIO14/
VLYNQ_TXD2
EM_A[16]/
GPIO15/
VLYNQ_RXD2
EM_A[15]/
GPIO16/
VLYNQ_TXD3
EM_A[14]/
GPIO17/
VLYNQ_RXD3
Table 2-9. EMIFA Terminal Functions (continued)
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
T2 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
T1 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
G3 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For EMIFA, it is read/write output EM_R/W.
F1 I/O/Z
IPU
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For EMIFA, it is wait state extension input EM_WAIT.
H4 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For EMIFA, it is output enable output EM_OE.
G2 I/O/Z
J3 I/O/Z
H2 I/O/Z
T3 I/O/Z
R3 I/O/Z
R4 I/O/Z
P5 I/O/Z
R2 I/O/Z
R5 I/O/Z
P3 I/O/Z
P4 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.
IPD
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For EMIFA, this is the Bank Address 0 output (EM_BA[0]).
When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of
the byte address.
When connected to a 16-bit asynchronous memory, this pin has the same function
as EMIF address pin 22 (EM_A[22]).
This pin is multiplexed between EMIFA, ATA/CF, and GPIO.
For EMIFA, this is the Bank Address 1 output EM_BA[1].
When connected to a 16 bit asynchronous memory this pin is the lowest order bit of
the 16-bit word address.
When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the
address.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 21 output EM_A[21].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 20 output EM_A[20].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 19 output EM_A[19].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 18 output EM_A[18].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 17 output EM_A[17].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 16 output EM_A[16].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 15 output EM_A[15].
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 14 output EM_A[14].
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