TMS320C6727B Datasheet, PDF (87/114 Pages) Texas Instruments – Floating-Point Digital Signal Processors

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370 – SEPTEMBER 2006
Table 4-31. Additional⁽¹⁾ SPI Master Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
MIN
MAX UNIT
18 t_{d(SPC_ENA)M}
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Max delay for slave to
deassert SPIx_ENA after ^{Polarity = 0, Phase = 1,}
final SPIx_CLK edge to ^{from SPIx_CLK falling}
ensure master does not
begin the next
transfer. ⁽⁴⁾
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
0.5t_c(SPC)M
0
ns
0.5t_c(SPC)M
0
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5t_c(SPC)M
20 t_{d(SPC_SCS)M}
Delay from final
SPIx_CLK edge to
master deasserting
SPIx_SCS ^{(5) (6)}
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
0
0.5t_c(SPC)M
ns
Polarity = 1, Phase = 1,
from SPIx_CLK rising
0
21 t_{d(SCSL_ENAL)M}
Max delay for slave SPI to drive SPIx_ENA valid
after master asserts SPIx_SCS to delay the
master from beginning the next transfer.
0.5P ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
2P – 10
Delay from SPIx_SCS
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5t_c(SPC)M + 2P – 10
22 t_{d(SCS_SPC)M}
active to first
SPIx_CLK ^{(7) (8) (9)}
Polarity = 1, Phase = 0,
to SPIx_CLK falling
2P – 10
ns
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5t_c(SPC)M + 2P – 10
Polarity = 0, Phase = 0,
to SPIx_CLK rising
3P + 15
23 t_{d(ENA_SPC)M}
Delay from assertion of
SPIx_ENA low to first
SPIx_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
0.5t_c(SPC)M + 3P + 15
ns
3P + 15
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5t_c(SPC)M + 3P + 15
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-27).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPIx_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx_ENA.
(8) In the case where the master SPI is ready with new data before SPIx_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPIx_ENA was initially deasserted high and SPIx_CLK is delayed.
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Peripheral and Electrical Specifications
87