TMS320C6727B Datasheet, PDF (8/114 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370 – SEPTEMBER 2006
www.ti.com
2.2 Enhanced C67x+ CPU
The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is
code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant
enhancements including an increase in core operating frequency from 225 MHz to 300 MHz⁽³⁾ while
operating at 1.2 V.
The CPU fetches 256-bit-wide advanced very-long instruction word (VLIW) fetch packets that are
composed of variable-length execute packets. The execute packets can supply from one to eight 32-bit
instructions to the eight functional units during every clock cycle. The variable-length execute packets are
a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. Additionally,
execute packets can now span fetch packets, providing a code size improvement over the C67x CPU
core.
The CPU features two data paths, shown in Figure 2-1, each composed of four functional units (.D, .M, .S,
and .L) and a register file. The .D unit in each data path is a data-addressing unit that is responsible for all
data transfers between the register files and the memory. The .M functional units are dedicated for
multiplies, and the .S and .L functional units perform a general set of arithmetic, logical, and branch
functions. All instructions operate on registers as opposed to data in memory, but results stored in the
32-bit registers can be subsequently moved to memory as bytes, half-words, or words.
Data Path A
Data Path B
Register File A
Cross
Paths
Register File B
.D1 .M1 .S1 .L1
.D2 .M2 .S2 .L2
Figure 2-1. CPU Data Paths
The register file in each data path contains 32 32-bit registers for a total of 64 general-purpose registers.
This doubles the number of registers found on the C67x CPU core, allowing the optimizing C compiler to
pipeline more complex loops by decreasing register pressure significantly.
The four functional units in each data path of the CPU can freely share the 32 registers belonging to that
data path. Each data path also features a single cross path connected to the register file on the opposing
data path. This allows each data path to source one cross-path operand per cycle from the opposing
register file. On the C67x+ CPU, this single cross-path operand can be used by two functional units per
cycle, an improvement over the C67x CPU in which only one functional unit could use the cross-path
operand. In addition, the cross-path register read(s) are not counted as part of the limit of four reads of the
same register in a single cycle.
The C67x+ CPU executes all C67x instructions plus new floating-point instructions to improve
performance specifically during audio processing. These new instructions are listed in Table 2-2.
(3) CPU speed is device-dependent. See Table 2-1.
8
Device Overview
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