TMS320C6727B Datasheet, PDF (100/114 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370 – SEPTEMBER 2006
www.ti.com
BYTE ADDRESS
0x4200 0088
0x4200 0090
0x4200 0094
0x4200 0098
0x4200 009C
0x4200 00A0
Table 4-38. RTI Registers (continued)
REGISTER NAME
RTIINTFLAG
RTIDWDCTRL
RTIDWDPRLD
RTIWDSTATUS
RTIWDKEY
RTIDWDCNTR
DESCRIPTION
Interrupt Flags. Interrupt pending bits.
Digital Watchdog Control. Enables the Digital Watchdog.
Digital Watchdog Preload. Sets the experation time of the Digital Watchdog.
Watchdog Status. Reflects the status of Analog and Digital Watchdog.
Watchdog Key. Correct written key values discharge the external capacitor.
Digital Watchdog Down-Counter
Figure 4-41 shows the bit layout of the CFGRTI register and Table 4-39 contains a description of the bits.
31
8
Reserved
7
6
4
3
2
0
Reserved
CAPSEL1
Reserved
CAPSEL0
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W, 0
Figure 4-41. CFGRTI Register Bit Layout (0x4000 0014)
Table 4-39. CFGRTI Register Bit Field Description (0x4000 0014)
BIT NO.
NAME
31:7,3
6:4
2:0
Reserved
CAPSEL1
CAPSEL0
RESET
VALUE
N/A
0
0
READ
WRITE
N/A
R/W
R/W
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
CAPSEL0 selects the input to the RTI Input Capture 0 function.
CAPSEL1 selects the input to the RTI Input Capture 1 function.
The encoding is the same for both fields:
000 = Select McASP0 Transmit DMA Event
001 = Select McASP0 Receive DMA Event
010 = Select McASP1 Transmit DMA Event
011 = Select McASP1 Receive DMA Event
100 = Select McASP2 Transmit DMA Event
101 = Select McASP2 Receive DMA Event
Other values are reserved and their effect is not determined.
100 Peripheral and Electrical Specifications
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