TMS320F28335_1 Datasheet, PDF (85/166 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

TMS320F28335, TMS320F28334, TMS320F28332
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Digital Signal Controllers (DSCs)
SPRS439B – JUNE 2007 – REVISED OCTOBER 2007
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-9, Table 4-10, and
Table 4-11.
Table 4-9. SCI-A Registers⁽¹⁾
NAME
SCICCRA
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA ⁽²⁾
SCIFFRXA ⁽²⁾
SCIFFCTA ⁽²⁾
SCIPRIA
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-10. SCI-B Registers^{(1) (2)}
NAME
SCICCRB
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB ⁽²⁾
SCIFFRXB ⁽²⁾
SCIFFCTB ⁽²⁾
SCIPRIB
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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Peripherals
85