TMS320VC5470ZHKA Datasheet, PDF (84/94 Pages) Texas Instruments – TMS320VC5470 Fixed-Point Digital Signal Processor

Electrical Specifications
6.14 ARM Clock Timings
The ARM SRAM timings are derived from the ARM clock. The clock switching characteristics are defined in
Table 6−33 for use in the ARM SRAM timing definitions.
Table 6−33. ARM SRAM Switching Characteristics
PARAMETER
MIN
TYP
MAX
A tc(ARM)
Cycle time, ARM clock
B tw(ARM−H)
Pulse duration, ARM clock high
C tw(ARM−L)
Pulse duration, ARM clock low
D tw(ARM−W)
Pulse duration, ARM write cycle
E tw(ARM−R)
Pulse duration, ARM read cycle
† _{A = tc(ARM)}
‡ _{n = the number of software wait states}
21.05
A/2 − 3†
A/2 − 3†
A/2†
A/2†
A/2 + nA†‡
A + nA†‡
A/2 + 3†
A/2 + 3†
UNIT
ns
ns
ns
ns
ns
The ARM SRAM write timing requirements listed in Table 6−34 represent back-to-back write operations to
a zero-wait-state SRAM device.
Table 6−34 through Table 6−35 assume testing over recommended operating conditions (see Figure 6−33
and Figure 6−34).
1 td(CSL-AV)
2 td(CSL-DV)
3 td(CSL-WEL)
4 tw(WEL)
5 td(WEH−AIV)
6 td(WEH−DIV)
7 td(WEH−DV)
8 tw(WEH)
9 td(WEH−CSH)
10 td(CSL−BEV)
11 td(WEH−BEIV)
12 td(WEH−BEV)
20 td(CSL-OEH)
21 td(WEH−OEL)
† _{A = tc(ARM)}
§ _{D = tw(ARM-W)}
Table 6−34. ARM SRAM Timing Requirements (Write)
MIN
Delay time, address valid from CS low
−3
Delay time, data valid from CS low
−2
Delay time, write enable low from CS low
Pulse width, write enable low
4
D − 3.5§
Delay time, address invalid from write enable high
0
Delay time, data invalid from write enable high
0
Delay time, data valid from write enable high
Pulse width, write enable high
2
A/2 − 3.5†
Delay time, CS high from write enable high
0
Delay time, byte enable valid from CS low
−3
Delay time, byte enable invalid from write enable high
0
Delay time, byte enable valid from write enable high
2
Delay time, output enable high from CS low
−3
Delay time, output enable low from write enable high
0
NOM
D§
A/2†
MAX
4
5
13
D + 3.5§
7
7
9
A/2 + 3.5†
7
4
7
9
4
7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
December 2001 − Revised December 2002
SPRS017B
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