TMS320VC5470ZHKA Datasheet, PDF (26/94 Pages) Texas Instruments – TMS320VC5470 Fixed-Point Digital Signal Processor

DSP Subsystem Functional Overview
This lists the 5470 DSP subsystem peripheral registers and describes those that are specific to the 5470 or
are different from the standard C54x registers. The standard C54x registers are defined in the
TMS320VC5409 Fixed-Point Digital Signal Processor data sheet (literature number SPRS082) and the
TMS320VC5402 Fixed-Point Digital Signal Processor data sheet (literature number SPRS079). The DSP
subsystem peripheral mapping is shown in Table 3−2.
NAME
DRR20
DRR10
DXR20
DXR10
TIM
PRD
TCR
–
SWWSR
BSCR
–
SWCR
–
SPSA0
SPSD0
–
GPIOCR
GPIOSR
–
DRR21
DRR11
DXR21
DXR11
–
SPSA1
SPSD1
–
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
–
Table 3−2. Peripheral Memory-Mapped Registers
ADDRESS
DESCRIPTION
20h
Data receive register 2
21h
Data receive register 1
22h
Data transmit register 2
23h
Data transmit register 1
24h
Timer register
25h
Timer period counter
26h
Timer control register
27h
Reserved
28h
Software wait-state register
29h
Bank-switching control register
2Ah
Reserved
2Bh
Software wait-state control register
2Ch−37h
Reserved
38h
McBSP0 subbank address register
39h
McBSP0 subbank data register
3Ah−3Bh
Reserved
3C
General-purpose I/O pins control register
3D
General-purpose I/O pins status register
3E−3F
Reserved
40h
Data receive register 2
41h
Data receive register 1
42h
Data transmit register 2
43h
Data transmit register 1
44h−47h
Reserved
48h
McBSP1 subbank address register
49h
McBSP1 subbank data register
4Ah−53h
Reserved
54h
DMA channel priority and enable control register
55h
DMA subbank address register
56h
DMA subbank data register with autoincrement
57h
DMA subbank data register
58h
Clock mode register
59h−5Fh
Reserved
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer
Timer
Timer
External Bus
External Bus, API
External Bus
McBSP #0
McBSP #0
GPIO
GPIO
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
DMA
DMA
DMA
DMA
PLL
December 2001 − Revised December 2002
SPRS017B
17