PCI4515 Datasheet, PDF (82/216 Pages) Texas Instruments – SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED

4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem vendor ID
40h (Function 0)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is
1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem ID
42h (Function 0)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register
The PCI4515 controller supports the index/data scheme of accessing the ExCA registers, which is mapped by this
register. An address written to this register is the address for the index register and the address+1 is the data address.
Using this access method, applications requiring index/data ExCA access can be supported. The base address can
be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See
the ExCA register set description in Section 5 for register offsets. All bits in this register are reset by GRST only.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
PC Card 16-bit I/F legacy-mode base-address
Type
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PC Card 16-bit I/F legacy-mode base-address
Type
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
PC Card 16-bit I/F legacy-mode base-address
44h (Function 0)
Read-only, Read/Write
0000 0001h
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