PCI4515 Datasheet, PDF (194/216 Pages) Texas Instruments – SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED

8.46 Isochronous Receive Context Match Register
The isochronous receive context match register starts an isochronous receive context running on a specified cycle
number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value.
The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8−35 for a
complete description of the register contents.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Isochronous receive context match
Type
RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW
Default X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous receive context match
Type
RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW
Default X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
BIT
31
30
29
28
27
26−12
11−8
7
6
5−0
Register:
Offset:
Type:
Default:
Isochronous receive context match
410Ch + (32 * n)
Read/Write, Read-only
XXXX XXXXh
Table 8−35. Isochronous Receive Context Match Register Description
FIELD NAME
tag3
tag2
tag1
tag0
RSVD
cycleMatch
sync
RSVD
tag1SyncFilter
channelNumber
TYPE
RW
RW
RW
RW
R
RW
RW
R
RW
RW
DESCRIPTION
If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b.
If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b.
If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b.
If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b.
Reserved. Bit 27 returns 0 when read.
This field contains a 15-bit value corresponding to the two low-order bits of cycleSeconds and the 13-bit
cycleCount field in the cycleStart packet. If cycleMatchEnable (bit 29) in the isochronous receive
context control register (see Section 8.44) is set to 1, then this context is enabled for receives when
the two low-order bits of the isochronous cycle timer register at OHCI offset F0h (see Section 8.34)
cycleSeconds field (bits 31−25) and cycleCount field (bits 24−12) value equal this field (cycleMatch)
value.
This 4-bit field is compared to the sync field of each isochronous packet for this channel when the
command descriptor w field is set to 11b.
Reserved. Bit 7 returns 0 when read.
If bit 6 and bit 29 (tag1) are set to 1, then packets with tag 01b are accepted into the context if the two
most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered
according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions.
If this bit is cleared, then this context matches on isochronous receive packets as specified in
bits 28−31 (tag0−tag3) with no additional restrictions.
This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA
context accepts packets.
8−44