PCI4515 Datasheet, PDF (47/216 Pages) Texas Instruments – SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED

Table 3−7. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
10h
Reserved
14h−1Ch
Socket power management
20h
3.6 Serial EEPROM Interface
The PCI4515 controller has a dedicated serial bus interface that can be used with an EEPROM to load certain
registers in the PCI4515 controller. The EEPROM is detected by a pullup resistor on the SCL terminal. See Table 3−9
for the EEPROM loading map.
3.6.1 Serial-Bus Interface Implementation
The PCI4515 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency
for standard mode I²C. The serial EEPROM must be located at address A0h.
Some serial device applications may include PC Card power switches, card ejectors, or other devices that may
enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed
in the sections that follow.
3.6.2 Accessing Serial-Bus Devices Through Software
The PCI4515 controller provides a programming mechanism to control serial bus devices through software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−8 lists the
registers used to program a serial-bus device through software.
PCI OFFSET
B0h
B1h
B2h
B3h
Table 3−8. PCI4515 Registers Used to Program Serial-Bus Devices
REGISTER NAME
DESCRIPTION
Serial-bus data
Contains the data byte to send on write commands or the received data byte on read commands.
Serial-bus index
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
Serial-bus slave
address
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W command selector are programmed through this register.
Serial-bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.6.3 Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−3.
The PCI4515 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I²C using
7-bit addressing.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown
in Figure 3−6. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−6. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
3−9