TAS1020B Datasheet, PDF (81/114 Pages) Texas Instruments – USB Streaming Controller

A.4.4.2 USB IN Endpoint – Y Buffer Base Address Byte (IEPBBAYx)
The USB IN endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location
for the Y data buffer for a particular USB IN endpoint.
Bit
Mnemonic
Type
7
BBAY10
R/W
6
BBAY9
R/W
5
BBAY8
R/W
4
BBAY7
R/W
3
BBAY6
R/W
2
BBAY5
R/W
1
BBAY4
R/W
0
BBAY3
R/W
BIT MNEMONIC
NAME
7:0 BBAY(10:3) Y Buffer base address
DESCRIPTION
The Y buffer base address value is set by the MCU to program the base address location in
memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address
location. This byte specifies the most significant 8 bits of the address. All 0s are used by the
hardware for the three least significant bits.
A.4.4.3 USB IN Endpoint – X Buffer Data Count Byte (IEPDCNTXx)
The USB IN endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received
in a data packet from the host PC. The no acknowledge status bit is also contained in this byte.
Bit
Mnemonic
Type
7
NACK
R/W
6
DCNTX6
R/W
5
DCNTX5
R/W
4
DCNTX4
R/W
3
DCNTX3
R/W
2
DCNTX2
R/W
1
DCNTX1
R/W
0
DCNTX0
R/W
BIT MNEMONIC
NAME
7 NACK
No acknowledge
6:0 DCNTX(6:0) X Buffer data count
DESCRIPTION
The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB IN
transaction to this endpoint to indicate that the USB endpoint X buffer is empty. For control,
interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the
endpoint result in a NACK handshake response to the host PC. Also for control, interrupt,
and bulk endpoints to enable this endpoint to transmit another data packet to the host PC,
this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake
response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to
sending the next data packet. However, the MCU or DMA must clear this bit after writing a
data packet to the buffer.
The X buffer data count value is set by the MCU or DMA when a new data packet is written
to the X buffer for the IN endpoint. The 7-bit value is set to the number of bytes in the data
packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples
in the data packet for isochronous endpoint transfers. To determine the number of samples
in the data packet for isochronous transfers, the bytes per sample value in the configuration
byte is used.
A.4.4.4 USB IN Endpoint – X and Y Buffer Size Byte (IEPBSIZx)
The USB IN endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers
to be used for this endpoint.
Bit
Mnemonic
Type
7
BSIZ7
R/W
6
BSIZ6
R/W
5
BSIZ5
R/W
4
BSIZ4
R/W
3
BSIZ3
R/W
2
BSIZ2
R/W
1
BSIZ1
R/W
0
BSIZ0
R/W
BIT MNEMONIC
NAME
7 BSIZ(7:0)
Buffer size
DESCRIPTION
For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the MCU
to program the size of the X and Y data packet buffers. Both buffers are programmed to the
same size based on this value. This value should be in 8 byte units. For example, a value of
18h results in the size of the X and Y buffers each being set to 192 bytes. For isochronous
transactions, the buffer size sets the size of the single circular buffer.
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