TAS1020B Datasheet, PDF (100/114 Pages) Texas Instruments – USB Streaming Controller

A.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 – Address FFDDh)
The codec port interface configuration register 4 is used to store various control bits for the codec port interface
operation.
Bit
Mnemonic
Type
Default
7
ATSL3
R/W
0
6
ATSL2
R/W
0
5
ATSL1
R/W
0
4
ATSL0
R/W
0
3
CPTBLK
R/W
0
2
DIVB2
R/W
0
1
DIVB1
R/W
0
0
DIVB0
R/W
0
BIT MNEMONIC
NAME
DESCRIPTION
7:4 ATSL(3:0)
Command/status address/data
time slot
The command/status address/data time slot bits are set by the MCU to program the
time slots to be used for the secondary communication address and data values. For
the AC ’97 modes of operation, this value must be set to 0001b which results in time
slot 1 being used for the address and time slot 2 being used for the data. For the AIC
and general-purpose modes of operation, the same time slot is used for both
address and data. For the AIC mode of operation this value must be set to 0111b
which results in time slot 7 being used for both the address and data.
0000b = time slot 0, 0001b = time slot 1, …, 1111b = time slot 15
3 CptBlk
C-port bulk mode
This bit is used when C-port is in Mode 0. If this bit is cleared to 0, the C-port
sync/clocks are free running once C-port is enabled. If this bit is set to 1, DMA
controls the C-port sync/clocks. The sync/clocks are active only when valid data is
present in a codec frame.
2:0 DIVB(2:0)
Divide by B value
The divide by B control bits are set by the MCU to program the divide ratio used to
derive CSCLK from MCLKO.
000b = CSCLK output disabled
001b = divide by 2
010b = divide by 3
011b = divide by 4
100b = divide by 5
101b = divide by 6
110b = divide by 7
111b = divide by 8
A–32