TLC2933A Datasheet, PDF (8/19 Pages) Texas Instruments – HIGH PERFORMANCE PHASE LOCKED LOOP

TLC2933A
HIGH PERFORMANCE PHASE LOCKED LOOP
SLES149 − OCTOBER 2005
operation characteristics, V_DD = 3.3 V, T_A = 25°C (unless otherwise noted) (continued)
PFD section
fmax
tPLZ
tPHZ
tPZL
tPZH
tr
tf
PARAMETER
Maximum operation frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
Fall time
TEST CONDITIONS
CL = 15 pF
CL = 15 pF
MIN
TYP
MAX
40
21
50
21
50
5.8
30
6.2
30
3
10
1.7
10
UNIT
MHz
ns
ns
ns
ns
ns
ns
electrical characteristics, V_DD = 5 V, T_A = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
VTH
High level output voltage
Low level output voltage
Input threshold voltage at select, VCO
inhibit
IOH = –2 mA
IOL = 2 mA
4
V
0.5
V
1.5
2.5
3.5
V
II
ZI(VCOIN)
IDD(inh)
Input current at select, VCO inhibit
VCO IN input impedance
VCO supply current (inhibit)
VI = VDD or GND
VCO IN = 1/2 VDD
See Note 16
±1
µA
10
M(
0.61
1
µA
IDD(vco) VCO supply current
See Note 17
35.5
55
mA
NOTES: 16. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited.
17. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and
PFD INHIBIT = GND.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
High level output voltage
IOH = –2 mA
4.5
VOL
Low level output voltage
IOL = 2 mA
IOZ
High impedance state output current
PFD inhibit = high, Vo = VDD or
GND
V
0.2
V
±1
µA
VIH
High level input voltage at Fin−A, Fin−B
4.5
V
VIL
Low level input voltage at Fin−A, Fin−B
1
V
VTH
Input threshold voltage at PFD inhibit
1.5
2.5
3.5
CIN
Input capacitance at Fin−A, Fin−B
5.6
pF
ZIN
Input impedance at Fin−A, Fin−B
10
MΩ
IDD(Z)
High impedance state PFD supply current See Note 18
1
µA
IDD(PFD) PFD supply current
See Note 19
0.48
3
mA
NOTES: 18. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
19. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, PFD
OUT open, and VCO OUT is inhibited
8
TI.COM