TLC2933A Datasheet, PDF (3/19 Pages) Texas Instruments – HIGH PERFORMANCE PHASE LOCKED LOOP

TLC2933A
HIGH PERFORMANCE PHASE LOCKED LOOP
SLES149 − OCTOBER 2005
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external register (R_BIAS) connected between the VCO V_DD
and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock
frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. Oscillation Frequency
VCO output frequency 1/2 divider
The TLC2933A SELECT terminal sets the f_OSC VCO output frequency as shown in Table 1. The 1/2 f_OSC output
should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
VCO inhibit function
SELLECT
Low
High
VCO OUTPUT
fOSC
1/2 fOSC
The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power−down mode as shown in Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
Low
High
PFD operation
VCO OSCILLATOR
Active
Stopped
VCO OUT
Active
Low level
IDD(VCO)
Normal
Power Down
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the
reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock
recovery PLL system, other types of phase detectors should be used.
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