SN74F161A_07 Datasheet, PDF (8/17 Pages) Texas Instruments – SYNCHRONOUS 4-BIT BINARY COUNTER

SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
Test
Point
500 Ω
From Output
Under Test
CL
(see Note A)
500 Ω ^S1
7V
Open
500 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
S1
Open
7V
Open
7V
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Input
tw
3V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Timing Input
1.5 V
0V
th
tsu
3V
Data Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
3V
1.5 V
0V
tPLH
In-Phase
Output
1.5 V
tPHL
VOH
1.5 V
VOL
tPHL
tPLH
Out-of-Phase
Output
1.5 V
1.5 V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
3V
1.5 V
1.5 V
0V
tPZL
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
tPLZ
≈3.5 V
VOL
+
0.3
V
VOL
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPHZ
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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