SN74F161A_07 Datasheet, PDF (5/17 Pages) Texas Instruments – SYNCHRONOUS 4-BIT BINARY COUNTER

SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Data
Outputs
QA
QB
QC
QD
RCO
12 13 14 15 0 1 2
Count
Sync Preset
Clear
Async
Clear
Inhibit
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