OPA2316 Datasheet, PDF (8/46 Pages) Texas Instruments – OPAx316 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier

OPA316, OPA2316, OPA2316S, OPA4316
SBOS703D – APRIL 2014 – REVISED DECEMBER 2014
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Electrical Characteristics (continued)
V_S (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
At T_A = 25°C, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
OUTPUT
V_S = 1.8 V, R_L = 10 kΩ, T_A= –40°C to 125°C
V_O
Voltage output swing from supply ^VS ^{= 5.5 V, R}L ^{= 10 kΩ, T}A^{= –40°C to 125°C}
rails
V_S = 1.8 V, R_L = 2 kΩ, T_A= –40°C to 125°C
V_S = 5.5 V, R_L = 2 kΩ, T_A= –40°C to 125°C
I_SC
Short-circuit current
V_S = 5 V
±50
Z_O
Open-loop output impedance
V_S = 5 V, f = 10 MHz
250
POWER SUPPLY
V_S
Specified voltage range
I_Q
Quiescent current per amplifier
Power-on time
SHUTDOWN (V_S = 1.8 V to 5.5 V)⁽²⁾
I_QSD
Quiescent current, per device
V_S = 5 V, I_O = 0 mA, T_A= –40°C to 125°C
V_S = 0 V to 5.5 V
All amplifiers disabled, SHDN = V_S–
One amplifier disabled (OPA2316S)
1.8
400
200
0.01
345
V_IH
High voltage (enabled)
V_IL
Low voltage (disabled)
t_ON
Amplifier enable time⁽³⁾
t_OFF
Amplifier disable time⁽³⁾
SHDN pin input bias current (per
pin)
TEMPERATURE
Amplifier enabled
Amplifier disabled
Full shutdown, G = 1, V_OUT = 0.9 × V_S / 2⁽⁴⁾
Partial shutdown, G = 1, V_OUT = 0.9 × V_S / 2⁽⁴⁾
G = 1, V_OUT = 0.1 × V_S / 2
V_IH = 5.0 V
V_IL = 0 V
(V+) – 0.5
13
10
5
3.5
2.5
Specified range
–40
T_A
Operating range
–55
T_stg
Storage range
–65
MAX
15
30
60
120
5.5
500
1
(V–) + 0.2
125
150
150
UNIT
mV
mV
mV
mV
mA
Ω
V
µA
µs
µA
µA
V
V
µs
µs
µs
pA
pA
°C
°C
°C
(2) Ensured by design and characterization; not production tested.
(3) Enable time (t_ON) and disable time (t_OFF) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2316S having both channels A and B disabled (SHDN_A = SHDN_B = V_S–). For partial shutdown,
only one SHDN pin is exercised; in partial mode, the internal biasing and oscillator remain operational and the enable time is shorter.
8
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