DRV8801-Q1_15 Datasheet, PDF (8/19 Pages) Texas Instruments – DMOS FULL-BRIDGE MOTOR DRIVERS

DRV8801-Q1
SLVSAS7A – FEBRUARY 2011 – REVISED JANUARY 2014
V_OUT+
V_OUT–
High-Z
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I_PEAK
I_OUTx ^IOCP
Enable
Source
or Sink
Charge Pump
Counter
nFAULT
t_DEG
t_OCP
Motor Lead
Short Condition
Figure 4. Overcurrent Control Timing
Normal DC
Motor Capacitance
FUNCTIONAL DESCRIPTION
Device Operation
The DRV8801-Q1 is designed to drive one dc motor. The current through the output full-bridge switches and all
N-channel DMOS are regulated with a fixed off-time PWM control circuit.
Logic Inputs
TI recommends using a high-value pullup resistor when logic inputs are pulled up to V_DD. This resistor limits the
current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and
ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.
VPROPI
This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times
greater than the motor winding current (VPROPI = 5 × I). VPROPI is meaningful only if there is a resistor
connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay,
VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, because at 500 mV on SENSE, the H-bridge is
disabled.
Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run
the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
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