DRV8801-Q1_15 Datasheet, PDF (12/19 Pages) Texas Instruments – DMOS FULL-BRIDGE MOTOR DRIVERS

DRV8801-Q1
SLVSAS7A – FEBRUARY 2011 – REVISED JANUARY 2014
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Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the low side
of the H-bridge (two sink drivers) and the load. Power dissipation I²R loses in the two sink DMOS drivers:
P_D = I² (2 ´ r_DS(on)Sink )
(2)
SENSE
A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To
minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an
independent ground return to the star ground point. This trace should be as short as possible. For low-value
sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
NOTE
When selecting a value for the sense resistor, SENSE does not exceed the maximum
voltage of ±500 mV. The H-bridge is disabled and enters recirculation while the motor
winding current generates a SENSE voltage greater than or equal to 500 mV.
Ground
A ground power plane should be located as close to the DRV8801-Q1 as possible. The copper ground plane
directly under the thermal pad makes a good location. This pad can then be connected to ground for this
purpose.
Layout
The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal
performance, the DRV8801-Q1 must be soldered directly onto the board. On the underside of the DRV8801-Q1
is a thermal pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered
directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. For
more information on this technique, see document SLMA002.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a
ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB,
connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in
order to minimize lead inductance.
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