CDC2510B Datasheet, PDF (8/10 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
SUPPLY VOLTAGE
400
fc = 100 MHz
350 CLY = CLF = 30 pF
TA = 25°C
300 _{Phase Error Measured}
from CLK to FBIN
250
200
150
100
50
0
–50
–100
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VCC – Supply Voltage – V
Figure 5
JITTER
vs
CLOCK FREQUENCY
400
VCC = 3.3 V
350
TA = 25°C
300
250
200
150
Peak to Peak
100
50
Cycle to Cycle
0
35 45 55 65 75 85 95 105 115 125
fc – Clock Frequency – MHz
Figure 6
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
16
14 ^{AVCC = 3.6 V}
Bias = 0/3 V
CLY = CLF = 30 pF
12
TA = 25°C
10
8
6
4
2
0
10 20 40 60 80 100 120 140
fc – Clock Frequency – MHz
Figure 7
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
VCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
200 _{TA = 25°C}
150
100
50
0
10 20 40 60 80 100 120 140
fc – Clock Frequency – MHz
Figure 8
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