CDC2510B Datasheet, PDF (7/10 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
50
250
40 ^{VCC = 3.3 V}
200
fc = 100 MHz
30 ^{CLY = 30pF}
150
TA = 25°C
Phase Error
20 ^{Phase Error Measured}
100
from CLK to Y
10
50
0
0
–10
–50
–20
–100
–30
Phase Adjustment Slope
–40
–150
–200
–50
–250
0 5 10 15 20 25 30 35 40 45 50
CLF – Lumped Feedback Capacitance at FBIN – pF
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
400
VCC = 3.3 V
CLY = CLF = 30 pF
300 ^{TA = 25°C}
Phase Error Measured
from CLK to FBIN
200
SCAS612 – SEPTEMBER 1998
100
0
–100
35 45 55 65 75 85 95 105 115 125
fc – Clock Frequency – MHz
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
Figure 4
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