CDC2510B Datasheet, PDF (5/10 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC, VCC
MIN TYP‡
VIK
II = –18 mA
3V
IOH = –100 µA
MIN to MAX VCC – 0.2
VOH
IOH = –12 mA
3V
2.1
IOH = – 6 mA
3V
2.4
IOL = 100 µA
MIN to MAX
VOL
IOL = 12 mA
3V
IOL = 6 mA
3V
II
ICC§
VI = VCC or GND
VI = VCC or GND,
IO = 0, Outputs: low or high
3.6 V
3.6 V
∆ICC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V
Ci
VI = VCC or GND
3.3 V
4
Co
VO = VCC or GND
3.3 V
6
‡ _{For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.}
§ _{For ICC of AVCC and ICC vs Frequency (see Figures 7 and 8).}
MAX
–1.2
0.2
0.8
0.55
±5
10
500
UNIT
V
V
V
µA
µA
µA
pF
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
fclk
Clock frequency
25 125 MHz
Input clock duty cycle
40% 60%
Stabilization time†
1 ms
† _{Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a}
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Note 6 and Figures 1 and 2)^‡
PARAMETER
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
± 0.165 V
MIN TYP MAX
VCC, AVCC = 3.3 V
± 0.3 V
MIN TYP MAX
UNIT
tphase _error, – jitter
(see Notes 7 and 8,
Figures 3, 4, and 5)
tsk(o)§
Jitter(pk-pk) (see Figure 6)
Jitter(cycle-cycle)
(See Figure 6)
CLKIN↑ = 66 MHz to 100 MHz
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
FBIN↑
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
–150
150 –200
–80
200 ps
200 ps
80
ps
|100|
Duty cycle reference
(see Figure 4)
F(clkin > 60 MHz)
Any Y or FBOUT
45%
55%
tr
Any Y or FBOUT
1.3 1.9 0.8
2.1 ns
tf
Any Y or FBOUT
1.7 2.5 1.2
2.7 ns
‡ _{These parameters are not production tested.}
§ _{The tsk(o) specification is only valid for equal loading of all outputs.}
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is – 230 ps to 230 ps for the 5% VCC range.
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