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CD74HC165 Datasheet, PDF (8/9 Pages) Texas Instruments – High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
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Test Circuits and Waveforms
tr
tf
CP OR CE
90%
10%
90%
Q7 OR Q7 10%
tW
1/fMAX
tPHL tPLH
tTLH
VS
GND
VS
tTHL
FIGURE 3. SERIAL-SHIFT MODE
PL
Q7 OR Q7
tW
tPHL
INPUT LEVEL
VS
tPLH
VS
FIGURE 4. PARALLEL-LOAD MODE
tr
INPUT D7
tPLH
Q7 OR Q7
90%
10%
90%
10%
tTHL
tf
INPUT LEVEL
GND
tPHL
VS
tTLH
FIGURE 5. PARALLEL-LOAD MODE
VALID
INPUTS D0-D7
tSU
tH
PL
VS
INPUT LEVEL
VS
GND
INPUT LEVEL
GND
FIGURE 6. PARALLEL-LOAD MODE
VALID
INPUTS DS
tSU
tH
CP OR CE
INPUT LEVEL
GND
INPUT LEVEL
GND
FIGURE 7. SERIAL-SHIFT MODE
PL
CP OR CE
VS
tREC
VS
INPUT LEVEL
GND
INPUT LEVEL
GND
FIGURE 8. SERIAL-SHIFT MODE
CE INHIBITED
CP
tSU
CE
tSU(L) tSU
CP
INHIBITED
tSU(L)
INPUT LEVEL
GND
INPUT LEVEL
GND
FIGURE 9. SERIAL-SHIFT, CLOCK-INHIBIT MODE
8
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