CD74HC165 Datasheet, PDF (7/9 Pages) Texas Instruments – High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

CD74HC165, CD74HCT165
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay
CP or CE to Q₇ or Q₇
PL to Q₇ or Q₇
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
C_L = 15pF
5
C_L = 50pF
6
t_PLH, t_PHL C_L = 50pF
2
4.5
25^oC
TYP MAX
-
165
-
33
13
-
-
28
-
175
-
35
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
205
250
ns
41
50
ns
-
-
ns
35
43
ns
220
265
ns
44
53
ns
D7 to Q₇ or Q₇
C_L = 15pF
5
14
-
-
C_L = 50pF
6
-
30
37
t_PLH, t_PHL C_L = 50pF
2
-
150
190
4.5
-
30
38
-
ns
45
ns
225
ns
45
ns
C_L = 15pF
5
12
-
-
C_L = 50pF
6
-
26
33
Output Transition Times
t_TLH, t_THL C_L = 50pF
2
-
75
95
4.5
-
15
19
-
ns
38
ns
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
Power Dissipation
Capacitance
(Notes 5, 6)
C_IN
-
-
-
10
10
C_PD
-
5
17
-
-
10
pF
-
pF
HCT TYPES
Propagation Delay
t_PLH, t_PHL C_L = 50pF
4.5
-
40
50
CP or CE to Q₇ or Q₇
C_L = 15pF
5
17
-
-
PL to Q₇ or Q₇
t_PLH, t_PHL C_L = 50pF
4.5
-
40
50
C_L = 15pF
5
17
-
-
D7 to Q₇ or Q₇
t_PLH, t_PHL C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
Input Capacitance
C_IN
C_L = 50pF
-
-
10
10
Power Dissipation
C_PD
-
5
24
-
Capacitance
(Notes 5, 6)
60
ns
-
ns
60
ns
-
ns
53
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
5. C_PD is used to determine the dynamic power consumption, per package.
6. P_D = V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
7