CD74HC165 Datasheet, PDF (2/9 Pages) Texas Instruments – High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

CD74HC165, CD74HCT165
Description
prevent shifting the data when PL goes HIGH.
The Harris CD74HC165 and CD74HCT165 are 8-bit parallel
or serial-in shift registers with complementary serial outputs
(Q₇ and Q₇) available from the last stage. When the parallel
load (PL) input is LOW, parallel data from the D0 to D7
inputs are loaded into the register asynchronously. When the
PL is HIGH, data enters the register serially at the DS input
and shifts one place to the right (Q₀→Q₁→Q₂, etc.) with
each positive-going clock transition. This feature allow paral-
lel-to-serial converter expansion by typing the Q₇ output to
the DS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
Ordering Information
TEMP. RANGE
PART NUMBER
(^oC)
PACKAGE
PKG. NO.
CD74HC165E
-55 to 125 16 Ld PDIP
E16.3
CD74HCT165E
-55 to 125 16 Ld PDIP
E16.3
CD74HC165M
-55 to 125 16 Ld SOIC M16.15
CD74HCT165M
-55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Functional Diagram
PARALLEL
DATA
INPUTS
11
D0
12
D1
13
D2
14
D3
3
D4
4
D5
5
D6
6
D7
DS ¹⁰
9
Q₇
7
Q₇
SERIAL
OUTPUTS
PL
CE
CP
1 15 2
GND = 8
VCC = 16
OPERATING MODE
Parallel Load
Serial Shift
Hold Do Nothing
TRUTH TABLE
INPUTS
Q_n REGISTER
OUTPUTS
PL
CE
CP
DS
D0 - D7
Q₀
Q₁ - Q₆
Q₇
Q₇
L
X
X
X
L
L
L-L
L
H
L
X
X
X
H
H
H-H
H
L
H
L
↑
l
X
L
q_{0 -} q₅
q₆
q₆
H
L
↑
h
X
H
q_{0 -} q₅
q₆
q₆
H
H
X
X
X
q₀
q_{1 -} q₆
q₇
q₇
2