CD74ACT297 Datasheet, PDF (8/12 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
fclock Clock frequency
tw
Pulse duration
tsu
Setup time before K CLK↑
th
Hold time after K CLK↑
K CLK
I/D CLK
K CLK
I/D CLK
D/U
ENCTR
D/U
ENCTR
TA = 25°C
MIN MAX
55
40
6
7
13
12
3
2
MIN MAX UNIT
45
MHz
35
8
ns
9
17
ns
16
7
ns
6
Carry Pulse
(Internal Signal)
Borrrow Pulse
(Internal Signal)
I/D CLK
I/D OUT
φB
φA2
92CS-40449
Figure 4. I/D OUT In Lock Condition
ECPD OUT
92CS-40450
Figure 5. Edge-Controlled Phase-Comparator Waveforms
8
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