CD74ACT297 Datasheet, PDF (10/12 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999
3V
φB
1.5 V
1.5 V
0V
3V
φA2
1.5 V
0V
ECPD OUT
tPHL
50% VCC 50% VCC
tPLH
≈VCC
VOL
92CS-43152
Figure 9. Waveforms Showing Phase Input (φB, φA2) to Output (ECPD OUT) Propagation Delays
tH
ÏÏÏ ÎÎÎÎÎÏÏÏÏ _D/U
ÏÏÏ ÎÎÎÎÎÏÏÏÏ ^ENCTR
ÏÏÏ ÎÎÎÎÎÏÏÏÏ tsu
1.5 V
1.5 V
1.5 V
tH
3V
1.5 V
0V
tsu
3V
K CLK
1.5 V
1.5 V
1.5 V
0V
tw
1/fmax
92CS-40453
NOTE A: Shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 10. Waveforms Showing Clock (K CLK) Pulse Duration and Maximum Clock Pulse Frequency,
and Inputs (D/U, ENCTR) to Clock (K CLK) Setup and Hold Times.
switching characteristics over recommended operating free-air temperature range, C_L = 50 pF,
(unless otherwise noted)
PARAMETER
fmax
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
FROM
(INPUT)
K CLK
I/D CLK
I/D CLK
φA2
φA1
φB
φB
TO
(OUTPUT)
I/D OUT
I/D OUT
ECPD OUT
XORPD OUT
XORPD OUT
ECPD OUT
TA = 25°C
MIN TYP MAX
55
40
19
19
24
17
17
17
17
24
MIN MAX UNIT
45
MHz
35
24
ns
24
30 ns
22
ns
22
22
ns
22
30 ns
10
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