BUF16821 Datasheet, PDF (8/29 Pages) EPCOS – Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory

BUF16821
SBOS428 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
GENERAL
The BUF16821 programmable voltage reference
allows fast and easy adjustment of 16 programmable
gamma reference outputs and two V_COM outputs,
each with 10-bit resolution. The BUF16821 is
programmed through a high-speed, I²C interface. The
final gamma and V_COM values can be stored in the
onboard, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
panel rework, the BUF16821 supports up to 16 write
operations to the onboard memory. The BUF16821
has two separate memory banks, allowing
simultaneous storage of two different gamma curves
to facilitate dynamic switching between gamma
curves.
The BUF16821 can be powered using an analog
supply voltage from 9V to 20V, and a digital supply
from 2V to 5.5V. The digital supply must be applied
before the analog supply to avoid excessive current
and power consumption, or possibly even damage to
the device if left connected only to the analog supply
for extended periods of time. Figure 10 illustrates a
typical configuration of the BUF16821.
TWO-WIRE BUS OVERVIEW
The BUF16821 communicates over an
industry-standard, two-wire interface to receive data
in slave mode. This standard uses a two-wire,
open-drain interface that supports multiple devices on
a single bus. Bus lines are driven to a logic low level
only. The device that initiates the communication is
called a master, and the devices controlled by the
master are slaves. The master generates the serial
clock on the clock signal line (SCL), controls the bus
access, and generates the START and STOP
conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a HIGH to a LOW logic level while SCL is HIGH.
All slaves on the bus shift in the slave address byte
on the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA LOW.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
HIGH. Any change in SDA while SCL is HIGH is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from LOW to HIGH while SCL is HIGH. The
BUF16821 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the
BUF16821.
ADDRESSING THE BUF16821
The address of the BUF16821 is 111010x, where x is
the state of the A0 pin. When the A0 pin is LOW, the
device acknowledges on address 74h (1110100). If
the A0 pin is HIGH, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
settings and BUF16821 address options.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 1. Quick-Reference of BUF16821 Addresses
DEVICE/COMPONENT
BUF16821 Address
A0 pin is LOW
(device acknowledges on address 74h)
A0 pin is HIGH
(device acknowledges on address 75h)
ADDRESS
1110100
1110101
COMMAND
General-Call Reset
High-Speed Mode
Table 2. Quick-Reference of Command Codes
CODE
Address byte of 00h followed by a data byte of 06h.
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
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