BUF16821 Datasheet, PDF (10/29 Pages) EPCOS – Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory

BUF16821
SBOS428 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com
DATA RATES
The two-wire bus operates in one of three speed
modes:
• Standard: allows a clock frequency of up to
100kHz;
• Fast: allows a clock frequency of up to 400kHz;
and
• High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
The BUF16821 is fully compatible with all three
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
mode, send a special address byte of 00001 xxx, with
SCL ≤ 400kHz, following the START condition; where
xxx are bits unique to the Hs-capable master, which
can be any value. This byte is called the Hs master
code. Table 2 provides a reference for the
High-speed mode command code. (Note that this
configuration is different from normal address
bytes—the low bit does not indicate read/write
status.) The BUF16821 responds to the High-speed
command regardless of the value of these last three
bits. The BUF16821 does not acknowledge this byte;
the
communication
protocol
prohibits
acknowledgement of the Hs master code. Upon
receiving a master code, the BUF16821 switches on
its Hs mode filters, and communicates at up to
3.4MHz. Additional high-speed transfers may be
initiated without resending the Hs mode byte by
generating a repeat START without a STOP. The
BUF16821 switches out of Hs mode with the next
STOP condition.
GENERAL-CALL RESET AND POWER-UP
The BUF16821 responds to a General-Call Reset,
which is an address byte of 00h (0000 0000) followed
by a data byte of 06h (0000 0110). The BUF16821
acknowledges both bytes. Table 2 provides a
reference for the General-Call Reset command code.
Upon receiving a General-Call Reset, the BUF16821
performs a full internal reset, as though it had been
powered off and then on. It always acknowledges the
General-Call address byte of 00h (0000 0000), but
does not acknowledge any General-Call data bytes
other than 06h (0000 0110).
When the BUF16821 powers up, it automatically
performs a reset. As part of the reset, the BUF16821
is configured for all outputs to change to the last
programmed nonvolatile memory values, or
1000000000 if the nonvolatile memory values have
not been programmed.
OUTPUT VOLTAGE
Buffer output values are determined by the analog
supply voltage (V_S) and the decimal value of the
binary input code used to program that buffer. The
value is calculated using Equation 1:
V_OUT = V_S ´
CODE₁₀
1024
(1)
The BUF16821 outputs are capable of a full-scale
voltage output change in typically 5µs; no
intermediate steps are required.
UPDATING THE DAC OUTPUT VOLTAGES
Because the BUF16821 features a double-buffered
register structure, updating the digital-to-analog
converter (DAC) and/or the V_COM register is not the
same as updating the DAC and/or V_COM output
voltage. There are two methods for updating the
DAC/V_COM output voltages.
Method 1: Method 1 is used when it is desirable to
have the DAC/V_COM output voltage change
immediately after writing to a DAC register. For each
write transaction, the master sets data bit 15 to a '1'.
The DAC/V_COM output voltage update occurs after
receiving the 16th data bit for the currently-written
register.
Method 2: Method 2 is used when it is desirable to
have all DAC/V_COM output voltages change at the
same time. First, the master writes to the desired
DAC/V_COM channels with data bit 15 a '0'. Then,
when writing the last desired DAC/V_COM channel, the
master sets data bit 15 to a '1'. All DAC/V_COM
channels are updated at the same time after
receiving the 16th data bit.
NONVOLATILE MEMORY
BKSEL Pin
The BUF16821 has 16x rewrite capability of the
nonvolatile memory. Additionally, the BUF16821 has
the ability to store two distinct gamma curves in two
different nonvolatile memory banks, each of which
has 16x rewrite capability. One of the two available
banks is selected using the external input pin,
BKSEL. When this pin is low, BANK0 is selected;
when this pin is high, BANK1 is selected.
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