BQ24350 Datasheet, PDF (8/17 Pages) Texas Instruments – Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET

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SLUS943A – MAY 2009 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
POWER DOWN
The device remains in power down mode when the input voltage at the ACIN pin is below the under-voltage
threshold V_UVLO. The FET Q1 and Q2 connected between ACIN and OUT pins are off.
POWER-ON RESET
The device resets when the input voltage at the ACIN pin exceeds the UVLO threshold. All internal counters and
other circuit blocks are reset. The IC then waits for duration t_BLK(CHGIN) for the input voltage to stabilize. If, after
t_BLK(CHGIN), the input voltage and battery voltage are in normal range, FET Q1 is turned ON. The IC has a
soft-start feature to control the inrush current. The soft-start minimizes the ringing at the input, where the ringing
occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant
circuit. Once the soft-start sequence starts, the IC monitors the load current. If the load current is larger than
I_O(OCP) for more than t_DGL(OCP), FET Q1 and Q2 are switched off. The IC then repeats the power-on sequence
after t_REC(OCP).
When a short-circuit is detected at power-on and Q1 is switched off, to prevent the input voltage from spiking up
due to resonance between the inductance of the input cable and the input capacitor, Q1 is turned off slowly by
reducing its gate-drive gradually, resulting in a “soft-stop”.
SLEEP MODE
When ACIN falls to below sleep mode entry threshold (V_SENTRY), the device operates in sleep mode and turns off
Q1 and Q2 by internal circuit regardless of the gate drive signal from GARDRV pin. The device exits sleep mode
when ACIN rising to above sleep mode exit threshold (V_SEXIT). In this way, the device behaves like a diode and
no external reverse blocking diode is needed in the application circuit.
OPERATING
The device continuously monitors the input voltage, the input current and the battery voltage as described in
detail below:
Input Over-Voltage Protection and LDO Mode Operation
The CHGIN output of the IC operates similar to a linear regulator. Figure 13 shows the typical input OVP
performance. When the ACIN input voltage is less than V_O(REG), and above the V_UVLO, the CHGIN output voltage
tracks the input voltage with a voltage drop caused by RDS(on) of the protection FET Q1. When the ACIN input
voltage is greater than V_O(REG) plus the RDS(on) drop of Q1, and less than V_OVP, the CHGIN output voltage is
regulated to V_O(REG), and this is also referred as LDO mode operation. If the input voltage rises above V_OVP, the
internal FET Q1 and Q2 are turned off after a blanking time of t_DGL(OVP), removing power from the circuit. When
the input voltage drops below V_OVP – V_HYS-OVP, and is still above V_UVLO, the FET Q1 and Q2 are turned on again
after a deglitch time of t_REC(OVP) , which ensures that the input supply is stabilized when the IC starts up again.
V_IN<V_OREG
V_IN>V_OREG
V_OVP
ACIN
V_POR
V_O(REG)
CHGIN
t_BLK(CHGIN)
t_DGL(OVP)
ACIN OVP
t_REC(OVP)
Figure 13. Input OVP Timing Diagram
Over Current Limiting and Protection
The device includes a low drop out linear current regulator. This current regulator uses Q1 as the controlling
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