BQ24350 Datasheet, PDF (4/17 Pages) Texas Instruments – Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET

bq24350
bq24352
SLUS943A – MAY 2009 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
Refer to the typical application circuit shown in Figure 1 . These specifications apply over ACIN=5V, T_J = -40~125°C, unless
otherwise specified. Typical values are at T_J = 25°C.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ACIN
V_UVLO
Under-voltage lock-out threshold
ACIN: 3V → 2V, ACIN falling
ACIN: 2V → 3V, ACIN rising
1.8 1.95
2.5
2.1
V
t_BLK(CHGIN) Input power on blanking time
I_DD
Operating current
INPUT TO OUTPUT CHARACTERISTICS
VACIN rising to CHGIN rising
No load on OUT and CHGIN pin
10
ms
500 µA
On resistance from ACIN to OUT
On resistance from ACIN to CHGIN
INPUT OVER-VOLTAGE PROTECTION (OVP)
I_OUT = 1.0A, ACIN=5V, GATDRV=0V
I_CHGIN = 1.0A, ACIN=5V, IOUT=0A
415 685 mΩ
250 495 mΩ
V_OREG
CHGIN voltage in LDO mode
ACIN=5.9V, GATDRV=CHGIN, ICHGIN=0 to
1A.
5.33 5.5 5.66
V
V_OVP
Input OVP threshold, bq24350
Input OVP threshold, bq24352
VACIN rising
6 6.17 6.35
V
6.9 7.1 7.3
Input OVP recovery hysteresis, bq24350
V_{HYS-OVP Input OVP recovery hysteresis, bq24352}
VACIN: 7.5V → 5V
250 300
100 150
350
mV
200
t_DGL(OVP) Input OVP deglitch time
VACIN rising to CHGIN falling
t_REC(OVP) Input OVP recovery time
VACIN falling below V_OVP to CHGIN rising
INPUT OVER CURRENT LIMITING AND PROTECTION (OCP)
256
µS
8.2
ms
I_O(OCP)
OCP threshold
t_DGL(OCP) OCP blanking time
t_REC(OCP) OCP recovery time
BATTERY OVER-VOLTAGE PROTECTION
1.02 1.2 1.38 A
8.2
ms
131
ms
BV_OVP
Battery OVP threshold
V_HYS-BOVP Battery OVP hysteresis
I_VBAT
VBAT pin leakage current
t_DGL(BOVP)
t_REC(BOVP)
CHGIN
Battery OVP deglitch time
Battery OVP recovery time
VBAT rising
VBAT falling
VBAT=4.25V, series connection of a 200kΩ
resistor, T_J = 25°C
VBAT rising to CHGIN falling
VBAT falling below BVOVP to CHGIN rising
4.3 4.35
200 250
8.2
131
4.4 V
300 mV
10 nA
ms
ms
V_SEXIT
Sleep mode exit threshold and CHGIN turn
on threshold, ACIN-VOUT
ACIN rising, VOUT = 4.2 V
24 90 160 mV
V_SENTRY
Sleep mode entry threshold and CHGIN turn
off threshold, ACIN-VOUT
ACIN falling, VOUT = 4.2 V
10 55 105 mV
I_DDSLP
Sleep Mode supply current
OUT = 4.2 V, GATDRV = 4.2 V,
ACIN = VSS
10 µA
R_DIS
CHGIN discharge resistor
Leakage current from OUT to CHGIN
INTEGRATED P-FET PARAMETERS
OUT = 4.2 V, GATDRV = 4.2 V, CHGIN = 0
V, ACIN = 0 V, T_J = 85°C
500
Ω
1 µA
Vt
Threshold Voltage, CHGIN-GATDRV.
CHGIN=5V, OUT=3.6V, I_OUT=10mA
Ig
GATDRV pin leakage current
500 680
0.1
800 mV
1 µA
Ioff
Off state leakage current at OUT pin.
ACIN=5V, GATDRV=CHGIN, OUT=0V
1
µA
Ronp
On Resistance of P-FET (from CHGIN to
OUT)
I_OUT = 1.0A, ACIN=5V, GATDRV=0V
165 225 mΩ
Gm
Forward Transconductance
Cg
Input capacitance at the GATDRV pin
ACIN=5V, I_OUT=5mA, GATDRV=3.5V
CHGIN=GATDRV=5V
27
mA/V
104
pF
THERMAL PROTECTION
4
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