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ADS7229 Datasheet, PDF (8/46 Pages) Texas Instruments – LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
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ADS7229
ADS7230
SBAS437 – MAY 2008........................................................................................................................................................................................................ www.ti.com
TIMING CHARACTERISTICS(1)(2) : 1.8V
All specifications typical at –40°C to 85°C, +VA = 2.7 V, and +VBD = 1.8V, unless otherwise noted.
fCCLK
t1
t2
tCL
t3
t4
t5
t6
tSCLKL
tSCLKH
tSCLK
tH2
tD1
tD2
tS1
tH1
tD3
t7
PARAMETER
Frequency, conversion clock, CCLK
Setup time, falling edge of CS to EOC
External, 3V ≤ +VA ≤ 3.6V,
fCCLK = 1/2 fSCLK
External, 2.7V ≤ +VA ≤ 3V,
fCCLK = 1/2 fSCLK
Internal,
fCCLK = 1/2 fSCLK
Hold time, falling edge of CS to EOC
Pulse duration, CONVST low
Hold time, falling edge of CS to EOS
Setup time, rising edge of CS to EOS
Hold time, rising edge of CS to EOS
Setup time, falling edge of CS to first t6 falling
SCLK
Pulse duration, SCLK low
Pulse duration, SCLK high
Cycle time, SCLK
All modes,
3V ≤ +VA ≤ 3.6V
All modes,
2.7V ≤ +VA < 3V
Hold time, falling edge of SCLK to SDO invalid 10pF Load
Delay time, falling edge of SCLK to SDO valid 10pF Load
Delay time, falling edge of CS to SDO valid,
SDO MSB output
10pF Load,
2.7V ≤ +VA ≤ 3V
10pF Load,
3V ≤ +VA ≤ 3.6V
Setup time, SDI to falling edge of SCLK
Hold time, SDI to falling edge of SCLK
Delay time, rising edge of CS/FS to SDO
3-state
Setup time, 16th falling edge of SCLK t7
before rising edge of CS/FS
ADS7229, ADS7230
MIN TYP
MAX UNIT
0.5
21
0.5
18.9 MHz
20
1
0
40
20
20
20
5
8
8
23.8
26.5
7.5
8
4
22.3
23.5
CCLK
ns
ns
ns
ns
ns
ns
tSCLK – 8 ns
tSCLK – 8 ns
2000
ns
2000
ns
16 ns
13
ns
11
ns
ns
8 ns
10
ns
(1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
8
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