XIO2213B Datasheet, PDF (79/199 Pages) Texas Instruments – PCI Express™ TO 1394b OHCI WITH 3-PORT PHY

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XIO2213B
PCI Express™ TO 1394b OHCI WITH 3-PORT PHY
SCPS210D – OCTOBER 2008 – REVISED JULY 2009
4.54 Link Control Register
The link control register controls link-specific behavior. See Table 4-30 for a complete description of the
register contents.
PCI register offset: A0h
Register type:
Read only, Read/Write
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
15:9 RSVD
8
CPM_EN
7
ES
6
CCC
5
RL
4
LD
3
RCB
2
RSVD
1:0 ASLPMC
Table 4-30. Link Control Register Description
ACCESS
RW
RW
RW
RW
R
R
RW
R
RW
DESCRIPTION
Reserved. Returns 00h when read.
Clock power management enable. This bit is used to enable XIO2213B to use CLKREQ
for clock power management
0 = Clock power management is disabled and XIO2213B shall hold the CLKREQ
signal low.
1 = Clock power management is enabled and XIO2213B is permitted to use the
CLKREQ signal to allow the REFCLK input to be stopped.
Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets
and an extra TS2 when exiting from L1 prior to entering to L0.
0 = Normal synch (default)
1 = Extended synch
Common clock configuration. When this bit is set, it indicates that the bridge and the
device at the opposite end of the link are operating with a common clock source. A value
of 0b indicates that the bridge and the device at the opposite end of the link are operating
with se te reference clock sources. The bridge uses this common clock configuration
information to report the correct L0s and L1 exit latencies.
0 = Reference clock is asynchronous (default).
1 = Reference clock is common.
Retrain link. This bit has no function and is read-only 0b.
Link disable. This bit has no function and is read-only 0b.
Read completion boundary. This bit is an indication of the RCB of the root complex. The
state of this bit has no effect on the bridge, since the RCB of the bridge is fixed at 128
bytes.
0 = 64 bytes (default)
1 = 128 bytes
Reserved. Returns 0b when read.
Active-state link PM control. This field enables and disables the active-state PM.
00 = Active-state PM disabled (default)
01 = L0s entry enabled
10 = L1 entry enabled
11 = L0s and L1 entry enabled
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Classic PCI Configuration Space
79