TMS320C5505 Datasheet, PDF (78/142 Pages) Texas Instruments – TMS320C5505 Fixed-Point Digital Signal Processor

TMS320C5505
SPRS660 – JANUARY 2010
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• 256-, 512-, 1024-, and 2048- word page sizes
• Burst lengths of 4 or 8
• Sequential burst type. Interleave burst type not supported.
• Auto initialization from reset
• Partial Array Self Refresh and Temperature Controlled Self Refresh modes
• Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip temperature
sensor
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Auto Precharge not supported for better Bank Interleaving performance
Additionally, the SDRAM/mSDRAM interface of EMIF supports placing the SDRAM/mSDRAM in
"Self-Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM/mSDRAM to be put into a
low-power state while still retaining memory contents; since the SDRAM/mSDRAM will continue to refresh
itself even without clocks from the DSP. Powerdown mode achieves even lower power, except the DSP
must periodically wake the SDRAM/mSDRAM up and issue refreshes if data retention is required. To
achieve the lowest power consumption, the SDRAM/mSDRAM interface has configurable slew rate on the
EMIF pins.
5.9.3 EMIF Peripheral Register Description(s)
Table 5-9 shows the EMIF registers.
Table 5-9. External Memory Interface (EMIF) Peripheral Registers⁽¹⁾
HEX ADDRESS
RANGE
1000h
1001h
1004h
1005h
1008h
1009h
100Ch
1010h
1011h
1014h
1015h
1018h
1019h
101Ch
101Dh
1020h
1021h
103Ch
1040h
1044h
1048h
104Ch
ACRONYM
REV
STATUS
AWCCR1
AWCCR2
SDCR1
SDCR2
SDRCR
ACS2CR1
ACS2CR2
ACS3CR1
ACS3CR2
ACS4CR1
ACS4CR2
ACS5CR1
ACS5CR2
SDTIMR1
SDTIMR2
SDSRETR
EIRR
EIMR
EIMSR
EIMCR
REGISTER NAME
Revision Register
Status Register
Asynchronous Wait Cycle Configuration Register 1
Asynchronous Wait Cycle Configuration Register 2
SDRAM/mSDRAM Configuration Register 1
SDRAM/mSDRAM Configuration Register 2
SDRAM/mSDRAM Refresh Control Register
Asynchronous CS2 Configuration Register 1
Asynchronous CS2 Configuration Register 2
Asynchronous CS3 Configuration Register 1
Asynchronous CS3 Configuration Register 2
Asynchronous CS4 Configuration Register 1
Asynchronous CS4 Configuration Register 2
Asynchronous CS5 Configuration Register 1
Asynchronous CS5 Configuration Register 2
SDRAM/mSDRAM Timing Register 1
SDRAM/mSDRAM Timing Register 2
SDRAM/mSDRAM Self Refresh Exit Timing Register
EMIF Interrupt Raw Register
EMIF Interrupt Mask Register
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
78
Peripheral Information and Electrical Specifications
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