TMS320C6670AXCYPA2 Datasheet, PDF (77/226 Pages) Texas Instruments – Multicore Fixed and Floating-Point System-on-Chip

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
www.ti.com
SPRS689D—March 2012
The BCx bit indicates the boot complete status of the corresponding CorePac. All BCx bits are sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.
Boot ROM code will be implemented such that each CorePac will set its corresponding BCx bit immediately before
branching to the predefined location in memory.
3.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by POR and will
survive all other device resets. See the Hardware Design Guide for KeyStone Devices in‘‘Related Documentation from
Texas Instruments’’ on page 66 for more information. The Power State Control Register is shown in Figure 3-9 and
described in Table 3-11.
Figure 3-9 Power State Control Register (PWRSTATECTL)
31
3
2
1
0
GENERAL_PURPOSE
HIBERNATION_MODE
HIBERNATION
STANDBY
RW, +0000 0000 0000 0000 0000 0000 0000 0
RW,+0
RW,+0
RW,+0
Legend: RW = Read/Write; -n = value after reset
Table 3-11 Power State Control Register Field Descriptions
Bit Field
31-3 GENERAL_PURPOSE
2
HIBERNATION_MODE
1
HIBERNATION
0
STANDBY
End of Table 3-11
Description
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Guide in2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.
Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
Indicates whether the device is in standby mode or not.
0 = Not in standby mode
1 = Standby mode
3.3.11 NMI Event Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6670 has
four NMIGRx registers (NMIGR0 through NMIGR3). The NMIGR0 register generates an NMI event to CorePac0,
the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a
NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI Event Generation to
CorePac Register is shown in Figure 3-10 and described in Table 3-12.
Figure 3-10 NMI Generation Register (NMIGRx)
31
1
0
Reserved
NMIG
R, +0000 0000 0000 0000 0000 0000 0000 000
RW,+0
Legend: RW = Read/Write; -n = value after reset
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Device Configuration 77