LM3S9792 Datasheet, PDF (733/1279 Pages) Texas Instruments – Stellaris® LM3S9792 Microcontroller

Stellaris® LM3S9792 Microcontroller
register. The status of the interrupt source is indicated by the I²S Raw Interrupt Status (I2SRIS)
register. The status of enabled interrupts is indicated by the I²S Masked Interrupt Status (I2SMIS)
register. The FIFO level interrupt has a second level of masking using the FFM bit in the I²S Transmit
Interrupt Status and Mask (I2STXISM) register.
The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field
in the I²S Transmit FIFO Level (I2STXLEV) register) is below the FIFO limit (programmed using
the I²S Transmit FIFO Limit (I2STXLIMIT) register) and both the TXSRIM and FFM bits are set. If
software attempts to write to a full FIFO, a Transmit FIFO Write error occurs (indicated by the
TXWERIS bit in the I²S Raw Interrupt Status (I2SRIS) register). The TXWERIS bit in the I2SRIS
register and the TXWEMIS bit in the I2SMIS register are cleared by setting the TXWEIC bit in the I²S
Interrupt Clear (I2SIC) register.
17.3.1.5
DMA Support
The µDMA can be used to more efficiently stream data to and from the I²S bus. The I²S tranmit and
receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the I2STXISM
register must be set for the request signaling to propagate to the µDMA module. See “Micro Direct
Memory Access (μDMA)” on page 246 for channel configuration.
The I²S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA
request is made, the µDMA controller transfers the number of items specified as the burst size for
the µDMA channel. Therefore, the µDMA channel burst size and the I²S FIFO service request limit
must be set to the same value (using the LIMIT field in the I2STXLIMIT register).
17.3.2
Receive
The receiver consists of a serial decoder, an 8-entry FIFO, and control logic. The receiver has
independent MCLK (I2S0RXMCLK), SCLK (I2S0RXSCK), and Word-Select (I2S0RXWS) signals.
17.3.2.1
Serial Decoder
The serial decoder accepts incoming audio stream data and places the sample data in the receive
FIFO. By configuring the serial decoder, common audio formats I²S, Left-Justified, and Right-Justified
are supported. The MSB is transmitted first. The sample size and system data size are configurable
with the SSZ and SDSZ bits in the I²S Receive Module Configuration (I2SRXCFG) register. The
sample size is the number of bits of data being received, and the system data size is the number
of I2S0RXSCK transitions between the word select transitions. The system data size must be large
enough to accommodate the maximum sample size. Any bits received after the LSB are 0s. If the
FIFO is full, the incoming sample (in Mono) or sample-pairs (Stereo) are dropped until the FIFO has
space. The serial decoder is enabled using the RXEN bit in the I2SCFG register.
17.3.2.2
FIFO Operation
The receive FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed
through the I²S Receive FIFO Data (I2SRXFIFO) register. Table 17-8 on page 734 defines the
interface for each Read mode. All data is stored MSB-aligned. The Stereo data is read left sample
then right.
In Mono mode, the FIFO interface can be configured to read the right or left channel by setting the
FIFO Mono Mode bit (FMM) in the I²S Receive FIFO Configuration (I2SRXFIFOCFG) register. This
enables reads from a single channel, where the channel selected can be either the right or left as
determined by the LRP bit in the I2SRXCFG register.
June 14, 2010
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