LM3S9792 Datasheet, PDF (293/1279 Pages) Texas Instruments – Stellaris® LM3S9792 Microcontroller

Stellaris® LM3S9792 Microcontroller
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status
is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error
occurs on a channel, that channel is automatically disabled by the μDMA controller. The other
channels are unaffected.
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ERRCLR
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
ERRCLR
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
0
μDMA Bus Error Status
Value Description
0 No bus error is pending.
1 A bus error is pending.
This bit is cleared by writing a 1 to it.
June 14, 2010
293
Texas Instruments-Advance Information