MSC1210 Datasheet, PDF (73/83 Pages) OKI electronic componets – Clock For 1/2 Duty VFD

MSC1210
www.ti.com
SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004
Summation Register 0 (SUMR0)
7
6
5
4
3
2
1
0
Reset Value
SFR E2h
00h
SUMR0
bits 7−0
Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.
Write: Will cause values in SUMR3−0 to be added to the summation register.
Read: Will clear the Summation Count Interrupt.
Summation Register 1 (SUMR1)
7
6
5
4
3
2
1
0
Reset Value
SFR E3h
00h
SUMR1
bits 7−0
Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8−15.
Summation Register 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E4h
00h
SUMR2
bits 7−0
Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16−23.
Summation Register 3 (SUMR3)
7
6
5
4
3
2
1
0
Reset Value
SFR E5h
00h
SUMR3
bits 7−0
Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31.
Offset DAC Register (ODAC)
7
6
5
4
3
2
1
0
Reset Value
SFR E6h
00h
ODAC
bits 7−0
bit 7
bit 6−0
Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset DAC
value is summed with the ADC input prior to conversion. Writing 00h or 80h to ODAC turns off the offset DAC.
Offset DAC Sign bit.
0 = Positive
1 = Negative
ǒ Ǔ Offset
+
*V_REF
2 @ PGA
@
ODAC^ƪ6 : 0^ƫ
127
@ (* 1)^bit7
NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals.
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