MSC1210 Datasheet, PDF (40/83 Pages) OKI electronic componets – Clock For 1/2 Duty VFD

MSC1210
SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004
Timer/Counter Control (TCON)
7
6
5
4
3
2
1
SFR 88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
www.ti.com
0
Reset Value
IT0
00h
TF1
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode.
bit 7
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
0: No Timer 1 overflow has been detected.
1: Timer 1 has overflowed its maximum count.
TR1
Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current count
bit 6
in TH1, TL1.
0: Timer is halted.
1: Timer is enabled.
TF0
Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode.
bit 5
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
0: No Timer 0 overflow has been detected.
1: Timer 0 has overflowed its maximum count.
TR0
Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current
bit 4
count in TH0, TL0.
0: Timer is halted.
1: Timer is enabled.
IE1
Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit
bit 3
will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will
inversely reflect the state of the INT1 pin.
IT1
Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts.
bit 2
0: INT1 is level triggered.
1: INT1 is edge triggered.
IE0
Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit
bit 3
will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will
inversely reflect the state of the INT0 pin.
IT0
Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts.
bit 2
0: INT0 is level triggered.
1: INT0 is edge triggered.
40