XIO2200A Datasheet, PDF (72/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
Classic PCI Configuration Space
4.47 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 00h indicating no additional capabilities are supported.
PCI register offset:
Register type:
Default value:
91h
Read-only
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
4.48 PCI Express Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4−24 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
92h
Read-only
0071h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
Table 4−24. PCI Express Capabilities Register Description
BIT FIELD NAME ACCESS
DESCRIPTION
15:9
RSVD
R
Reserved. Returns 000 0000b when read.
8
SLOT
R
Slot implemented. This bit is not valid for the bridge and is read-only 0b.
7:4
DEV_TYPE
R
Device/port type. This read-only field returns 0111b indicating that the device is a PCI
Express-to-PCI bridge.
3:0
VERSION
R
Capability version. This field returns 1h indicating revision 1 of the PCI Express capability.
March 5 2007 − June 2011
SCPS154C
59