XIO2200A Datasheet, PDF (146/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
1394 OHCI Memory-Mapped Register Space
8.7 Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM,
offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents.
OHCI register offset:
Register type:
Default value:
18h
Read/Write
0000 XXXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE X X X X X X X X X X X X X X X X
BIT
31−24
23−16
15−0
FIELD NAME
info_length
crc_length
rom_crc_value
Table 8−6. Configuration ROM Header Register Description
TYPE
RW
DESCRIPTION
IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 0h.
RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 8.16) is set to 1b. The default value for this field is 0h.
RW IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 8.16) is set to 1b.
8.8 Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the
constant 3133 3934h, which is the ASCII value of 1394.
OHCI register offset:
Register type:
Default value:
1Ch
Read-only
3133 3934h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
1
1
1
0
0
1
0
0
1
1
0
1
0
0
March 5 2007 − June 2011
SCPS154C 133