XIO2200A Datasheet, PDF (133/203 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY

Not Recommended for New Designs
1394 OHCI—PCI Configuration Space
7.15 MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15−8 in the
latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6,
Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, then the contents of this
register are loaded through the serial EEPROM interface. If no serial EEPROM is detected, then this register
returns a default value that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 7−11 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
3Eh
Read/Update
0402h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0
Table 7−11. MIN_GNT and MAX_LAT Register Description
BIT FIELD NAME TYPE
DESCRIPTION
15−8† MAX_LAT
RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the OHCI controller. The default for this register indicates that the OHCI controller may need to access
the PCI bus as often as every 0.25 μs; thus, an extremely high priority level is requested. Bits 11−8 of this
field may also be loaded through the serial EEPROM.
7−0† MIN_GNT
RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the OHCI controller. The default for this register indicates that the OHCI controller may need to sustain
burst transfers for nearly 64 μs and thus request a large value be programmed in bits 15−8 of the OHCI
controller latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see
Section 7.6, Latency Timer and Class Cache Line Size Register). Bits 3−0 of this field may also be loaded
through the serial EEPROM.
† _{These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.}
7.16 OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and
provides a bit for big endian PCI support. See Table 7−12 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
40h
Read/Write, Read-only
0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT
31−1
0
FIELD NAME
RSVD
GLOBAL_SWAP
Table 7−12. OHCI Control Register Description
TYPE
R
RW
DESCRIPTION
Reserved. Bits 31−1 return 000 0000 0000 0000 0000 0000 0000 0000b when read.
When bit 0 is set to 1b, all quadlets read from and written to the PCI interface are byte-swapped (big
endian). The default value for this bit is 0b which is little endian mode.
120 SCPS154C
March 5 2007 − June 2011