LM3S9B95 Datasheet, PDF (718/1282 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte
Received (FBR) bit is set only after the Stellaris^® device detects its own slave address and receives
the first data byte from the I²C master. The Receive Request (RREQ) bit indicates that the Stellaris^®
I²C device has received a data byte from an I²C master. Read one data byte from the I²C Slave
Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit indicates that the
Stellaris^® I²C device is addressed as a Slave Transmitter. Write one data byte into the I²C Slave
Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris^® I²C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FBR TREQ RREQ
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
Name
reserved
FBR
TREQ
Type
RO
RO
RO
Reset Description
0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
First Byte Received
Value Description
1 The first byte following the slave’s own address has been
received.
0 The first byte has not been received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0
Transmit Request
Value Description
1
The I²C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
0 No outstanding transmit request.
718
June 14, 2010
Texas Instruments-Advance Information