LM3S9B95 Datasheet, PDF (371/1282 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

Stellaris® LM3S9B95 Microcontroller
Figure 10-4. SDRAM Write Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
NOP
AD [15:0] driven out
NOP
Column-1
Write
Data 0
Data 1
...
AD [15:0] driven out
Data n
Burst
Term
10.4.2
Host Bus Mode
Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051devices and
SRAM devices. This interface is asynchronous and uses strobe pins to control activity.
10.4.2.1
Control Pins
The main three strobes are ALE (Address latch enable), WRn (write), and RDn (sometimes called
OEn, used for read). Note that the timings are designed for older logic and so are hold-time vs.
setup-time specific. To ensure proper operation on this bus, the EPI block uses two system clocks
per transition to allow significant skewing of control vs. data signals. So, for example, ALE rises one
EPI clock before ADDR/DATA is asserted. Likewise, ALE falls (latch point) one EPI clock before
DATA changes or tri-states. The same approach is used for the WRn and RDn/OEn strobes. The
polarity of the read and write strobes can be active high or active low by clearing or setting the
RDHIGH and WRHIGH bits in the EPI Host-Bus n Configuration 2 (EPIHBnCFG2) register.
The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFG2 register.
The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared.
All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an
external latch to capture the address then hold it until the data phase. CSn is best used for Host-Bus
unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the
address and data phases of a read or write access is occurring. Both the ALE and the CSn modes
can be enhanced to access two external devices using settings in the EPIHBnCFG2 register. Wait
states can be added to the data phase of the access using the WRWS and RDWS bits in the
EPIHBnCFG2 register.
For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and
output to what the XFIFO can handle.
Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1 or
2 external devices to the EPI signals as well as control whether byte select signals are provided in
HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG
register, the CSCFG field in the EPIHBnCFG2 register, and the BSEL bit in the EPIHB16CFG register.
June 14, 2010
371
Texas Instruments-Advance Information