TC341 Datasheet, PDF (7/17 Pages) Texas Instruments – 780X488 PIXEL CCD IMAGE SENSOR

TC341
780×488 PIXEL
CCD IMAGE SENSOR
SOCS083A – OCTOBER 2002
advanced lateral overflow drain
The advanced overflow drain structure is shared by two neighboring pixels in each line. Varying the dc bias of
the antiblooming drain controls the blooming protection level and trades it for well capacity. Applying a pulse
(approximately 10 V above the nominal level for a minimum of 1 µs) to the drain removes all charge from the
pixels. This feature permits a precise control of the integration time on a frame-by-frame basis. The single-pulse
clearing capability also reduces smear by eliminating accumulated charge in the pixels before the start of the
integration period (single-sided smear). The application of a negative 1-V pulse to the antiblooming drain during
the parallel transfer is recommended. This pulse prevents creation of undesirable artifacts caused by the
on-chip crosstalk between the image area gate clock lines and the antiblooming drain bias lines.
serial register
The serial register is used to transport charge stored in the pixels of the memory to the output amplifier. The
register well capacity is designed to hold two complete lines of data. This allows implementation of pixel
summing in the vertical direction (line summing) and thus also implementation of pseudo-interlace. This is
accomplished by summing together lines 1+2, 3+4, … in one field and lines 2+3, 4+5, … in the other. The true
interlace is obtained by skipping appropriate lines in each field and dumping unwanted charge into a clearing
drain. The clearing drain is located next to the serial register and charge is directed to it via a special charge
transfer gate (TRG).
charge detection node
The last element of the charge readout chain is the charge detection node. The charge detection used in this
device is based on a floating diffusion (FD) concept. The n+ FD node serves as a capacitor that is first reset
to a suitable reference voltage. Charge from the serial register pixel is then transferred on the node. This causes
a change in the potential of FD, and a gate of the first stage source follower transistor connected to it senses
this change. The output signal from the first stage is further buffered by another source follower stage to provide
necessary driving capability for the off-chip circuits.
The reset gate of the detection node reset transistor is connected to its own pin. This allows more flexibility in
operating the sensor. By skipping the reset pulses, charge from several pixels can be summed together. This
feature also allows an easy implementation of correlated double sampling (CDS) that is used to minimize the
undesirable effect of reset (kTC) noise.
The detection node is reset to a voltage reference that is generated internally on-chip and tracks the process
induced potential variations. This improves the accuracy and stability of the device operation.
special feature
The sensor is provided with a charge input structure located at the upper right-hand corner of the image-sensing
array. Charge input may be useful for a variety of applications, but its main purpose here is electrical testing of
the sensor during manufacturing.
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