SN74CB3T16210 Datasheet, PDF (7/14 Pages) Texas Instruments – 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

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SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
Input Generator
50 Ω
V_G1
Input Generator
50 Ω
V_G2
V_IN
50 Ω
V_I
50 Ω
V_CC
DUT
TEST CIRCUIT
V_O
C_L
(see Note A)
R_L
R_L
2 × V_CC
S1
Open
GND
TEST
t_pd(s)
t_PLZ/t_PZL
t_PHZ/t_PZH
V_CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
S1
Open
Open
2 × V_CC
2 × V_CC
Open
Open
R_L
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
V_I
3.6 V or GND
5.5 V or GND
GND
GND
3.6 V
5.5 V
C_L
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
V_∆
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(V_IN)
V_CC/2
V_CC
V_CC/2
0V
Output
Control
(V_IN)
V_CC/2
V_CC/2
V_CC
0V
t_PLH
t_PHL
Output
V_CC/2
V_OH
V_CC/2
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t_pd(s))
Output
Waveform 1
S1 at 2 × V_CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t_PZL
t_PZH
V_CC/2
V_CC/2
t_PLZ
V_CC
V_OL + V_∆
t_PHZ
V_OL
V_OH
V_OH - V_∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r ≤ 2.5 ns, t_f ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
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