DS90C185 Datasheet, PDF (7/19 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

AC Timing Diagrams
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FIGURE 1. “Worst Case” Test Pattern (Note 7)
FIGURE 2. “16 Grayscale” Test Pattern - DS90C185 (Note 8, Note 9)
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Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS I/O.
Note 8: Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power
consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (CLK).
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