DS90C185 Datasheet, PDF (13/19 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

Functional Description
DS90C185 converts a wide parallel LVCMOS input bus into
FPD-Link LVDS data. The device can be configured to sup-
port RGB-888 (24 bit color) or RGB-666 (18 bit color). The
DS90C185 has several power saving features including: se-
lectable VOD, 18 bit / 24 bit mode select, and a power down
pin control.
In each input pixel clock cycle, data from D[27:0] is serialized
and driven out on TxOUT[3:0] +/- with TxCLKOUT +/-. If
18B_MODE is LOW, then TxOUT3 +/- is powered down and
the corresponding LVCMOS input signals are ignored.
The input pixel clock can range from 25 MHz to 105 MHz,
resulting in a total maximum payload of 700 Mbps (28 bits *
25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver
will operate at a speed of 7 bits per input clock cycle, resulting
in a serial line rate of 175 Mbps to 735 Mbps. TxCLKOUT +/-
will operate at the same rate as CLK with a duty cycle ratio of
57:43.
Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS
data is latched on. If RFB is HIGH, input data is latched on
the RISING EDGE of the pixel clock (CLK). If RFB is LOW,
the input data is latched on the FALLING EDGE of the pixel
clock. Note: This can be set independently of receiver’s output
clock strobe.
RFB
0
1
TABLE 1. Pixel Clock Edge
Result
FALLING edge
RISING edge
Power Management
The DS90C185 has several features to assist with managing
power consumption. The 18B_MODE pin allows the
DS90C185 to power down the unused LVDS driver for
RGB-666 (18 bit color) applications. If no clock is applied to
the CLK pin, the DS90C185 will enter a low power state. To
place the DS90C185 in its lowest power state, the device can
be powered down by driving the PDB pin to LOW.
Sleep Mode (PDB)
The DS90C185 provides a power down feature. When the
device has been powered down, current draw through the
supply pins is minimized and the PLL is shut down. The LVDS
drivers are also powered down with their outputs pulled to
GND through 100Ω resistors.
TABLE 2. Power Down Select
PDB Result
0
SLEEP Mode (default)
1
ACTIVE (enabled)
LVDS Outputs
The DS90C185's LVDS drivers are compatible with ANSI/
TIA/EIA-644–A LVDS receivers. The LVDS drivers an output
a power saving low V_OD or a higher V_OD to enable longer trace
and cable lengths by configuring the VODSEL pin.
TABLE 3. VOD Select
VODSEL Result
0
±180 mV (360mVpp)
1
±300 mV (600mVpp)
For more information regarding the electrical characteristics
of the LVDS outputs, refer to the LVDS DC Characteristics
and LVDS Switching Specifications.
18 bit / 24 bit Color Mode (18B)
The 18B pin can be used to further save power by powering
down the 4th LVDS driver in each used bank when the appli-
cation requires only 18 bit color or 3D+C LVDS. Set the 18B
pin to logic HIGH to TRI-STATE® TxOUT3 +/-. For 24 bit color
applications this pin should be set to logic LOW. Note that the
power down function takes priority over the TRI-STATE®
function.
TABLE 4. Color DepthConfigurations
18B_Mode Result
0
24bpp, LVDS 4D+C
1
18bpp, LVDS 3D+C
LVCMOS Inputs
The DS90C185 has 28 data inputs. These inputs are typically
used for 24 or 18 bits of RGB video with 1, 2 or 3 video control
signal (HS, VS and DE) inputs and one spare bit that can be
used for L/R signaling or function as a general purpose bit. All
LVCMOS input pins are designed for 1.8V LVCMOS logic. All
LVCMOS inputs, including clock, data and configuration pins
have an internal pull down resistor to set a default state. If any
LVCMOS inputs are unused, they can be left as no connect
(NC) or connected to ground.
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