CF45538NSRG4 Datasheet, PDF (7/19 Pages) Texas Instruments – TIRIS RF-Module IC for Automotive

www.ti.com
Function and Operation
(*) In both transmit and receive modes, this RF-module IC modulates and demodulates signals by logical
operation based on the incorporated master clock. This means that the modulating-demodulating
performance characteristics of this IC are directly affected by the frequency accuracy and variation of its
master clock (normal frequency is 17.1776 MHz). Therefore, the user is requested to select an oscillating
element or an external clock which is compatible with the remote TIRIS transponder to be used (see the
section describing the specifications “fexc”, “fL” and “fH”).
6.2 Sending Mode
In the Sending Mode, the frequency of the IC master clock (normal value: 17.1776 MHz) is divided by 128.
The resulting clock signal then has a frequency of 134.2 kHz (normal value). This resulting signal is output
as a composite signal for “TXHI” and “TXLO” terminals (pins) to drive the MOSFET which is incorporated
as an antenna resonance circuit driver, as illustrated below.
RI45538NS
TXLO TXHI
7
8
MOSFET(PCH)
Master clock frequency divided by 128
(Ref. frequency, resulting: 134.2 kHz)
"A"
MOSFET(NCH)
When the IC is in the Receiving Mode, its “TXHI” terminal is fixed at positive level and the “TXLO” at high
impedance. As a result, the output terminal “A” of the MOSFET used as an antenna resonance circuit
driver is fixed at negative level.
Note that when the IC is in the Sending Mode, its “RXDT–“ terminal is always fixed at positive level and as
a consequence, the IC’s FSK signal demodulator remains deactivated although data clock signals, which
are transmitted at a frequency resulting from division of the “A3IN” terminal signal frequency by 16, are
output to the “RXCK”.
6.3 Receiving Mode
In the Receiving Mode, the frequency-shift-keyed data signals are sequentially digitized to discriminate
their frequencies by binary notation (high-low) and demodulate them into bit strings consisting of bit data
“1” and “0”.
For binary discrimination of signal frequencies between high and low, the frequency level of each
FS-keyed signal is measured from its leading edge at the “A3OP” terminal through to the next leading
edge by count of the internal master clock, as shown below. The threshold for this counted value (x in the
diagram below) is fixed at 132; when the clock count is over 132, it results in a negative level output at the
“RXDT–“ terminal (bit data ”1”), and when the clock count does not reach 132, a positive level output at
the same terminal (bit data “0”), respectively.
Internal master clock
Signals discriminated
at A3OP terminal
Clock counts
123456
X-1 X 1 2 3 4 5 6 7
SCBU036 – December 1996
Submit Documentation Feedback
TIRIS RF-Module IC for Automotive
7