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CF45538NSRG4 Datasheet, PDF (11/19 Pages) Texas Instruments – TIRIS RF-Module IC for Automotive
www.ti.com
Input-Output Specifications
ITEM
Delay time between TXCT– and TX trailing edges
Delay time between TXCT– and TX leading edges
TX cycle time
TX low level pulse duration
TX high level pulse duration
SIGNAL
tdl(TX)
tdh(TX)
tc(TX)
twl(TX)
twh(TX)
MIN
TYP
128Tc(OSC)
64Tc(OSC)
64Tc(OSC)
MAX
64Tc(OSC)
1Tc(OSC)
UNIT
nS
nS
nS
nS
nS
Note: “Tc(osc)" denotes the master clock cycle of this RF-module IC and its normal value is specified at
56.3 ns (1/0.0171776). The same applies hereinafter. “TX” is defined as a composite signal of “TXLO” and
“TXHI” signals.
8.2 Receiver Signal I/O Timing
A3OP
RXCK
ts(RXDT)
twh(A3OP)
tdh(RXCK)
twh(RXCK)
td(RXDT)
tdl(RXCK)
th(RXDT)
tc(A3OP)
RXDT-
tc(RXCK)
tw(RXDT)
DATA VALID
ITEM
A3OP cycle time for normal FSK signal demodulation
A3OP positive level pulse duration for normal FSK signal
demodulation
A3OP cycle time for negative level output of RXDT–
signal (bit data “1”)
Delay time between A3OP and RXCK leading edges
Delay time between A3OP leading edge and RXCK
trailing edge
RXCK cycle time
RXCK positive level pulse duration
Delay time from consecutive A3OP identical signal
waves to definition of an RXDT– signal
RXDT– positive/negative level duration, definite
RXDT– signal setup time in relation to RXCK signal
RXDT– signal hold time in relation to RXCK signal
SIGNAL
tc(A3OP)
twh(A3OP)
tc(A3OP)
tdh(RXCK)
tdl(RXCK)
tc(RXCK)
twh(RXCK)
td(RXDT)
tw(RXDT)
ts(RXDT)
th(RXDT)
MIN
2Tc(OSC)
1Tc(OSC)
TYP
MAX
132Tc(OSC)
1Tc(OSC)
1Tc(OSC)
16Tc(A3)
8Tc(A3)
16Tc(A3)+1Tc(OSC)
4Tc(A3)—1Tc(OSC
)
4Tc(A3)–1Tc(OSC)
16Tc(A3)
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SCBU036 – December 1996
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TIRIS RF-Module IC for Automotive
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